View HB286075A1_340617.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
75 Mega Byte Flash ATA Card 60 Mega Byte Flash ATA Card 45 Mega Byte Flash ATA Card 30 Mega Byte Flash ATA Card 15 Mega Byte Flash ATA Card
ADE-203-623B (Z) Rev. 2.0 Feb. 28, 1997 Description
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1 are Flash ATA card. This card complies with PC card ATA standard and is suitable for the usage of data storage memory medium for PC or any other electric equipment. This card is equipped with Hitachi 64 Mega bit Flash memory HN29W6411. This card is suitable for ISA (Industry Standard Architecture) bus interface standard ,and read/write unit is 1 sector (512 bytes) sequential access. By using this card it is possible to operate good performance for the system which have PC card slots.
Features
* PC card ATA standard specification 68 pin two pieces connector and type II (5 mm) * 5V single power supply operation * ISA standard and Read/Write unit is 512 bytes (sector) sequential access Sector Read/Write transfer rate: 8MB/sec burst High reliability based on internal ECC (Error Correcting Code) function * Card density is 75 Mega bytes maximum This card is equipped Hitachi 64 Mega bit Flash memory (HN29W6411) * Internal self-diagnostic program operates at VCC power on
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
* * * * High reliability based on wear leveling function Data write endurance is 100,000 cycle (min) per logical sector. Data reliability is 1 error in 10 14 bits read. Auto Sleep Function
Card Line Up
Type No. HB286015A1 HB286030A1 HB286045A1 HB286060A1 HB286075A1 Card density 15 MB 30 MB 45 MB 60 MB 75 MB
2
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Card Pin Assignment
Memory card mode I/O card mode Pin NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Signal name I/O GND D3 D4 D5 D6 D7 -CE1 A10 -OE -- A9 A8 -- -- -WE +READY VCC -- -- -- -- I/O I/O I/O I/O I/O I I I -- I I -- -- I O -- -- -- -- Signal name I/O GND D3 D4 D5 D6 D7 -CE1 A10 -OE -- A9 A8 -- -- -WE -IREQ VCC -- -- -- -- I/O I/O I/O I/O I/O I I I -- I I -- -- I O -- -- -- -- Pin NO. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Memory card mode I/O card mode Signal name I/O GND -CD1 D11 D12 D13 D14 D15 -CE2 VS1 RFU RFU -- -- -- -- -- VCC -- -- -- -- O I/O I/O I/O I/O I/O I O -- -- -- -- -- -- -- -- -- -- -- Signal name I/O GND -CD1 D11 D12 D13 D14 D15 -CE2 VS1 -IORD -IOWR -- -- -- -- -- VCC -- -- -- -- O I/O I/O I/O I/O I/O I O I I -- -- -- -- -- -- -- -- --
3
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Memory card mode I/O card mode Pin NO. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal name I/O -- A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 +WP GND -- I I I I I I I I I/O I/O I/O O -- Signal name I/O -- A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 -IOIS16 GND -- I I I I I I I I I/O I/O I/O O -- Pin NO. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Memory card mode I/O card mode Signal name I/O -- -- VS2 +RESET -WAIT RFU -REG BVD2 BVD1 D8 D9 D10 -CD2 GND -- -- O I O -- I O O I/O I/O I/O O -- Signal name I/O -- -- VS2 +RESET -WAIT -INPACK -REG -SPKR -STSCHG D8 D9 D10 -CD2 GND -- -- O I O O I O O I/O I/O I/O O --
Card Pin Explanation
Address bus (A0 to A10: input): Address bus is A0 to A10. A0 is invalid in word mode. A10 is MSB and A0 is LSB. Data bus (D0 to D15: input/output): Data bus is D0 to D15. D0 is the LSB of the Even Byte of the Word. D8 is the LSB of the Odd Byte of the Word. Card enable (-CE1, -CE2: input): -CE1 and -CE2 are low active card select signals. Even addresses are controlled by -CE1 and odd addresses are by -CE2. Output enable (-OE: input): -OE is used for the control of data read in Attribute area or Common memory Task File area. Write enable (-WE: input): -WE is used for the control of data write in Attribute memory area or Common memory Task File area. I/O read (-IORD: input): -IORD is used for control of read data in I/O Task File area. This card dose not respond to -IORD until I/O card interface setting up. I/O write (-IOWR: input): -IOWR is used for control of data write in I/O Task File area. This card dose not respond to -IOWR until I/O card interface setting up.
4
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Ready/Busy, Interrupt request (+READY, -IREQ: output): In I/O card mode, this signal is -IREQ pin. The signal of low level indicates that the card is requesting software service to host, and high level indicates that the card is not requesting. In memory card mode, the signal is +READY pin. +READY pin turns low level during the card internal initialization operation at VCC applied or reset applied, so next access to the card should be after the signal turned high level. Card detection (-CD1, -CD2: output): -CD1 and -CD2 are the card detection signals. -CD1 and -CD2 are connected to ground in this card, so HOST can detect that the card is inserted or not. These signal lines should be pulled up to V CC through over 10k resistance by the host interface. Write protect, 16 bit I/O port (+WP, -IOIS16: output): In memory card mode, +WP is held low because this card dose not have write protect switch. In I/O card mode, -IOIS16 is asserted that a 16-bit or odd byte only operation can be performed at the addressed port. Attribute memory area selection (-REG: input): -REG should be high level during common memory area accessing, and low level during Attribute area accessing. Attribute memory area is located only even address, so D0 to D7 are valid and D8 to D15 are invalid in the word access mode. Odd addresses are invalid in the byte access mode. The signal must also be asserted during I/O cycles when the I/O address is on the bus. Battery voltage detection, Digital audio output (BVD2, -SPKR: output): In memory card mode, BVD2 outputs the battery voltage status in the card. This card has no battery, so this output is high level constantly. In I/O card mode, -SPKR is held High because this card dose not have digital audio output. Reset (+RESET: input): By assertion of +RESET signal, all registers of this card are cleared and +READY signal turns to high level when the internal initialization is completed. Wait (-WAIT: output): This signal outputs low level for delaying completion of memory access cycle or I/O access cycle. Input acknowledge (-INPACK: output): This signal outputs low level when -CE and -IORD is low level and card I/O port is responding to address which on the address bus. This signal is used for the input data buffer control. Battery voltage detection, Status change (BVD1, -STSCHG: output): In memory card mode, BVD1 outputs the battery voltage status in the card. This card has no battery, so this output is high level constantly. In I/O card mode, -STSCHG is asserted low to alert the host changes in the Ready/Busy states. Its use is controlled by configuration and status register. VCC voltage sense (VS1, VS2: output): This signals are intended to notify the socket of PC Card's CIS VCC requirement. VS1 and VS2 are nonconnected in this card.
5
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Card Block Diagram
VCC GND
internal VCC
local address bus
local data bus control signal
A0 to A10 -CE1,-CE2 -OE -WE -IORD -IOWR -REG +RESET D0 to D15 Controller control signal
DRAM
HN29W6411
+READY/-IREQ +WP/-IOIS16 -INPACK BVD1/-STSCHG -WAIT control signal control signal
Micro processor
VS1 VS2
OPEN OPEN Reset IC VCC
Oscillator
BVD2/-SPKR -CD1 -CD2
Note: -CE2, -CE1, -OE, -WE, -IORD, -IOWR, -REG, +RESET are pulled up in card. -CE2, -CE1, -OE, -WE, -IORD, -IOWR, -REG, +RESET pin are schmitt trigger type input buffer.
6
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Card Function Explanation
Register construction * Attribute region Configuration register * Configuration Option register * Configuration and Status register * Pin Replacement register * Socket and Copy register CIS (C ard Information S tructure) * Task File region Data register Error register Feature register Sector Count register Sector Number register Cylinder Low register Cylinder High register Drive Head register Status register Alternate Status register Command register Device Control register Drive Address register
7
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Host access specifications 1. Attribute access specifications When CIS-ROM region or Configuration register region is accessed, read and write operations are executed under the condition of -REG = "L" as follows. That region can be accessed by Byte/Word/ Odd-byte modes which are defined by PC card standard specifications. Attribute Read Access Mode
Mode Standby mode Byte access (8-bit) -REG x L L Word access (16-bit) Odd byte access (8-bit) Note: x: L or H L L -CE2 H H H L L -CE1 H L L L H A0 x L H x x -OE x L L L L -WE x H H H H D8 to D15 High-Z High-Z High-Z invalid invalid D0 to D7 High-Z even byte invalid even byte High-Z
Attribute Write Access Mode
Mode Standby mode Byte access (8-bit) -REG x L L Word access (16-bit) Odd byte access (8-bit) Note: x: L or H L L -CE2 H H H L L -CE1 H L L L H A0 x L H x x -OE x H H H H -WE x L L L L D8 to D15 Don't care Don't care Don't care Don't care Don't care D0 to D7 Don't care even byte Don't care even byte Don't care
Attribute Access Timing Example
A0 to A10 -REG -CE2/-CE1 -OE -WE D0 to D15 read cycle Dout Din
write cycle
8
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
2. Task File register access specifications
There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address area. Each case of Task File register read and write operations are executed under the condition as follows. That area can be accessed by Byte/Word/Odd Byte mode which are defined by PC card standard specifications.
(1) I/O address map Task File Register Read Access Mode (1)
Mode Standby mode Byte access (8-bit) -REG -CE2 x L L Word access (16-bit) Odd byte access (8-bit) Note: x: L or H L L H H H L L -CE1 H L L L H A0 x L H x x -IORD -IOWR -OE x L L L L x H H H H x H H H H -WE x H H H H D8 to D15 D0 to D7 High-Z High-Z High-Z odd byte odd byte High-Z even byte odd byte even byte High-Z
Task File Register Write Access Mode (1)
Mode Standby mode Byte access (8-bit) -REG -CE2 x L L Word access (16-bit) Odd byte access (8-bit) Note: x: L or H L L H H H L L -CE1 H L L L H A0 x L H x x -IORD -IOWR -OE x H H H H x L L L L x H H H H -WE x H H H H D8 to D15 D0 to D7 Don't care Don't care Don't care even byte Don't care odd byte odd byte odd byte even byte Don't care
Task File Register Access Timing Example (1)
A0 to A10 -REG -CE2/-CE1 -OE -WE D0 to D15 read cycle Dout Din
write cycle
9
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
(2) Memory address map Task File Register Read Access Mode (2)
Mode Standby mode Byte access (8-bit) -REG -CE2 x H H Word access (16-bit) Odd byte access (8-bit) Note: x: L or H H H H H H L L -CE1 H L L L H A0 x L H x x -OE x L L L L -WE x H H H H -IORD -IOWR D8 to D15 D0 to D7 x H H H H x H H H H High-Z High-Z High-Z odd byte odd byte High-Z even byte odd byte even byte High-Z
Task File Register Write Access Mode (2)
Mode Standby mode Byte access (8-bit) -REG -CE2 x H H Word access (16-bit) Odd byte access (8-bit) Note: x: L or H H H H H H L L -CE1 H L L L H A0 x L H x x -OE x H H H H -WE x L L L L -IORD -IOWR D8 to D15 D0 to D7 x H H H H x H H H H Don't care Don't care Don't care even byte Don't care odd byte odd byte odd byte even byte Don't care
Task File Register Access Timing Example (2)
A0 to A10 -REG -CE2/-CE1 -OE -WE D0 to D15 read cycle Dout Din
write cycle
10
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Configuration register specifications This card supports four Configuration registers for the purpose of the configuration and observation of this card. 1. Configuration Option register (Address 200H) This register is used for the configuration of the card configuration status and for the issuing soft reset to the card.
bit7 SRESET bit6 LevlREQ bit5 INDEX bit4 bit3 bit2 bit1 bit0
Note: initial value: 00H
Name SRESET (HOST->)
R/W R/W
Function Setting this bit to "1", places the card in the reset state (Card Hard Reset). This operation is equal to Hard Reset, except this bit is not cleared. Then this bit set to "0", places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset) . Card configuration status is reset and the card internal initialized operation starts when Card Hard Reset is executed, so next access to the card should be the same sequence as the power on sequence. This bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode interrupt is selected. This bits is used for select operation mode of the card as follows. When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose of Memory card interface recognition.
LevlREQ (HOST->) INDEX (HOST->)
R/W R/W
INDEX bit assignment
INDEX bit 5 0 0 0 0 4 0 0 0 0 3 0 0 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 1 Card mode Memory card I/O card I/O card I/O card Task File register address 0H to FH, 400H to 7FFH xx0H to xxFH 1F0H to 1F7H, 3F6H to 3F7H 170H to 177H, 376H to 377H Mapping mode memory mapped contiguous I/O mapped primary I/O mapped secondary I/O mapped
11
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
2. Configuration and Status register (Address 202H) This register is used for observing the card state.
bit7 CHGED bit6 SIGCHG bit5 IOIS8 bit4 0 bit3 0 bit2 PWD bit1 INTR bit0 0
Note: initial value: 00H
Name CHGED (CARD->) SIGCHG (HOST->)
R/W R
Function This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to "1". When CHGED bit is set to "1", -STSCHG pin is held "L" at the condition of SIGCHG bit set to "1" and the card configured for the I/O interface. This bit is set or reset by the host for enabling and disabling the status-change signal (STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", STSCHG pin is controlled by CHGED bit. If this bit is set to "0", -STSCHG pin is kept "H". The host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus (D7 to D0). When this bit is set to "1", the card enters sleep state (Power Down mode). When this bit is reset to "0", the card transfers to idle state (active mode). RRDY/-BSY bit on Pin Replacement Register becomes BUSY when this bit is changed. RRDY/-BSY will not become Ready until the power state requested has been entered. This card automatically powers down when it is idle, and powers back up when it receives a command. This bit indicates the internal state of the interrupt request. This bit state is available whether I/O card interface has been configured or not. This signal remains true until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the -IEN bit in the Device Control Register, this bit is a zero.
R/W
IOIS8 (HOST->) PWD (HOST->)
R/W R/W
INTR (CARD->)
R
12
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
3. Pin Replacement register (Address 204H)
This register is used for providing the signal state of -IREQ signal when the card configured I/O card interface. bit7 0 bit6 0 bit5 bit4 bit3 1 bit2 1 bit1 bit0
CRDY/-BSY 0
RRDY/-BSY 0
Note: initial value: 0CH
Name
R/W
Function This bit is set to "1" when the RRDY/-BSY bit changes state. This bit may also be written by the host. When read, this bit indicates +READY pin states. When written, this bit is used for CRDY/-BSY bit masking.
CRDY/-BSY R/W (HOST->) RRDY/-BSY R/W (HOST->)
4. Socket and Copy register (Address 206H) This register is used for identification of the card from the other cards. Host can read and write this register. This register should be set by host before this card's Configuration Option register set.
bit7 0 bit6 0 bit5 0 bit4 DRV# bit3 0 bit2 0 bit1 0 bit0 0
Note: initial value: 00H
Name DRV# (HOST->)
R/W R/W
Function This fields are used for the configuration of the plural cards.
13
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
CIS informations CIS informations are defined as follows. By reading attribute address from "000H", card CIS informations can be confirmed.
Address Data 7 000H 002H 004H 01H 04H 65 4 3 2 1 0 Description of contents Device info tuple Link length is 4 byte CIS function Tuple code Link to next tuple
CISTPL DEVICE TPL_LINK
DFH Device type
W Device speed Device type = DH: I/O device Device type, WPS, speed P WPS = 0: No WP S Device speed = 7: ext speed Speed exponent 2k units 400 ns if no wait 2k byte of address space End of device Other conditions device info tuple Link length is 5 bytes VCC MWAIT 5 V, wait is not used Extended speed Device size END marker Tuple code Link to next tuple Other conditions info field
006H 008H 00AH 00CH 00EH 010H 012H
4AH EXT Speed mantissa 01H 1x
FFH List end marker 1CH CISTPL DEVICE OC 05H 00H TPL_LINK EXT Reserved
DFH Device type
W Device speed Device type = DH: I/O device Device type, WPS, speed P WPS = 0: No WP S Device speed = 7: ext speed Speed exponent 2k units 400 ns if no wait 2k byte of address space End of device Other conditions device info tuple Link length is 4 bytes VCC MWAIT 5 V, wait is used Extended speed Device size END marker Tuple code Link to next tuple Other conditions info field
014H 016H 018H 01AH 01CH 01EH 020H
4AH EXT Speed mantissa 01H 1x
FFH List end marker 1CH CISTPL DEVICE OC 04H 01H TPL_LINK EXT Reserved
D2H Device type
W Device speed Device type = DH: I/O device Device type, WPS, speed P WPS = 0: No WP S Device speed = 2: 200 ns 2k units 2k byte of address space End of device JEDEC ID common memory Link length is 2 bytes Device size END marker Tuple code Link to next tuple JEDEC ID of PC Card ATA
022H 024H 026H 028H 02AH 02CH
01H
1x
FFH List end marker 18H 02H CISTPL JEDEC C TPL_LINK
DFH PCMCIA's manufacturer's JEDEC Manufacturer's ID code ID code 01H PCMCIA JEDEC device code 2nd byte of JEDEC ID
14
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Address Data 7 02EH 030H 032H 034H 036H 038H 03AH 03CH 03EH 040H 20H 04H 07H 00H 00H 00H 21H 02H 04H 01H 65 4 3 2 1 0 Description of contents Manufacturer's ID code Link length is 4 bytes HITACHI JEDEC manufacturer's ID CIS function Tuple code Link to next tuple Low byte of manufacturer's ID code CISTPL MANFID TPL_LINK Low byte of PCMCIA manufacturer's code High byte of PCMCIA manufacturer's code Low byte of product code High byte of product code CISTPL MANFID TPL_LINK TPLFID_FUNCTION = 04H Reserved RP Function ID tuple Link length is 2 bytes
Code of 0 because other byte High byte of manufacturer's is JEDEC 1 byte manufac ID ID code HITACHI code for PC CARD Low byte of product code ATA High byte of product code Tuple code Link to next tuple
Disk function, may be silicon, PC card function code may be removable R = 0: No BIOS ROM P = 1: Configure card at power on Function extension tuple Link length is 2 bytes System initialization byte
042H 044H 046H 048H 04AH 04CH 04EH 050H
22H 02H 01H 01H 22H 03H 02H
CISTPL FUNCE TPL_LINK
Tuple code Link to next tuple Extension tuple type for disk Interface type Tuple code Link to next tuple Extension tuple type for disk Basic ATA option parameters byte 1
Disk function extension tuple type Disk interface type Disk interface type CISTPL FUNCE TPL_LINK PC card ATA interface Function extension tuple Link length is 3 bytes
Disk function extension tuple type Single drive DUSV No VPP , silicon, single drive V = 0: No V PP required S = 1: Silicon U = 1: Unique serial # D = 1: Single drive on card
0CH Reserved
052H
0FH R
I
E N P3 P2 P1 P0
P0: Sleep mode supported Basic ATA option parameters P1: Standby mode supported byte 2 P2: Idle mode supported P3: Drive auto control N: Some config excludes 3X7 E: Index bit is emulated I: Twin IOIS16# data reg only R: Reserved
15
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Address Data 7 054H 056H 058H 65 4 3 2 1 0 Description of contents Configuration tuple Link length is 5 bytes RAS RFS: Reserved RMS: TPCC_RMSK sze - 1 =0 i RAS: TPCC_RADR sze - 1 =1 i 1 byte register mask 2 byte config base address CIS function Tuple code Link to next tuple Size of fields byte TPCC_SZ 1AH CISTPL CONF 05H 01H TPL LINK RFS RMS
05AH 05CH
03H 00H
TPCC_LAST TPCC RADR (LSB)
Entry with config index of 3 is Last entry of config registers final entry in table Configuration registers are located at 200 H in REG space Location of config registers
05EH 060H
02H
TPCC RADR (MSB) SPCI I: CCOR, C: CCSR P: PRR, S: SCR Configuration registers present mask TPCC_RMSK
0FH Reserved
16
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Address Data 7 062H 064H 066H 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 8 bytes Memory mapped I/O configuration I = 1: Interface byte follows D = 1: Default entry Configuration index = 0 W = 0: Wait not used R = 1: Ready active P = 0: WP not used B = 0: BVD1 and BVD2 not used IF type = 0: Memory interface CIS function Tuple code Link to next tuple Configuration table index byte TPCE_INDX 1BH CISTPL_CFTABLE ENTRY 08H TPL_LINK D Configuration index
C0H I
068H
40H
W
RP
B Interface type
Interface description field TPCE_IF
06AH
A1H M
MS
IR IO T P
Feature selection byte M = 1: Misc info present MS = 01: Memory space info TPCE_FS single 2-byte length IR = 0: No interrupt info present IO = 0: No I/O port info present T = 0: No timing info present P = 1: V CC only info Nominal voltage only follows Power parameters for VCC R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Nominal voltage = 5 V VCC nominal value
06CH
01H
R
DI PI AI SI HV LV NV
06EH 070H 072H 074H
55H 08H 00H 20H
X
Mantissa
Exponent
Length in 256 bytes pages (LSB) Length in 256 bytes pages (MSB) X R P RO A T
Length of memory space is 2 Memory space description kB structures (TPCE MS)
Miscellaneous features field X = 0: No more misc fields TPCE_MI R: Reserved P = 1: Power down supported RO = 0: Not read only mode A = 0: Audio not supported T = 0: Single drive
17
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Address Data 7 076H 078H 07AH 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 10 bytes CIS function Tuple code Link to next tuple 1BH CISTPL_CFTABLE ENTRY 0AH TPL_LINK C1H I D Configuration INDEX
Contiguous I/O mapped ATA Configuration table index byte TPCE_INDX registers configuration I = 1: Interface byte follows D = 1: Default entry Configuration index = 1 W = 0: Wait not used R = 1: Ready active P = 0: WP not used B = 0: BVS1 and BVD2 not used IF type = 1: I/O interface Interface description field TPCE_IF
07CH
41H
W
RP
B interface type
07EH
99H
M
MS
IR IO T P
Feature selection byte M = 1: Misc info present MS = 00: No memory space TPCE_FS info IR = 1: Interrupt info present IO = 0: No I/O port info present T = 0: No timing info present P = 1: V CC only info Nominal voltage only follows Power parameters for VCC R: Reserved DI: Power down Current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Nominal voltage = 5 V VCC nominal value
080H
01H
R
DI PI AI SI HV LV NV
082H 084H
55H 64H
X R
Mantissa
Exponent
S E IO AddrLine
S = 1: 16-bit hosts supported I/O space description field E = 1: 8-bit hosts supported TPCE_IO IO AddrLine: 4 lines decoded N Interrupt request description S = 1: Share logic active structure P = 1: Pulse mode IRQ TPCE_IR supported L = 1: Level mode IRQ supported M = 1: Bit mask of IRQs present V = 0: No vender unique IRQ B = 0: No bus error IRQ I = 0: No IO check IRQ N = 0: No NMI
086H
F0H
S
PL
MVBI
18
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Address Data 7 088H 65 4 3 2 1 0 Description of contents CIS function FFH IRQ IR IR IR IR IR IR IRQ0 7 QQQQQQ 654321 FFH IRQ IR IR IR IR IR IR IRQ8 15 Q Q Q Q Q Q 14 13 12 11 10 9 20H X R P RO A T IRQ level to be routed 0 to 15 Mask extension byte 1 recommended TPCE_IR Recommended routing to any Maskextension byte 2 "normal, maskable" IRQ. TPCE_IR Miscellaneous features field X = 0: Nomore misc fields TPCE_MI R: reserved P = 1: Power down supported RO = 0: Not read only mode A = 0: Audio not supported T = 0: Single drive
08AH
08CH
19
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Address Data 7 08EH 090H 092H 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 12 bytes ATA primary I/O mapped configuration I = 1: Interface byte follows D = 0: No default entry Configuration index = 2 W = 0: Wait not used R = 1: Ready active P = 0: WP not used B = 0: BVS1 and BVD2 not used IF type = 1: I/O interface CIS function Tuple code Link to next tuple Configuration table index byte TPCE_INDX 1BH CISTPL_CFTABLE ENTRY 0CH TPL_LINK 82H I D Configuration INDEX
094H
41H
W
RP
B interface type
Interface description field TPCE_IF
096H
18H
M
MS
IR IO T P
M = 0: No misc info present Feature selection byte MS = 00: No memory space TPCE_FS info IR = 1: Interrupt info present IO = 0: No I/O port info present T = 0: No timing info present P = 0: No V CC info I/O space description field R = 1: Range follows S = 1: 16-bit hosts supported TPCE_IO E = 1: 8-bit hosts supported IO AddrLines: 10 lines decoded LS = 1: Size of lengths is 1 I/O range format description byte AS = 2: Size of address is 2 byte N Range = 1: Address range - 1 1st I/O base address (LSB) 1st I/O base address (MSB) 1st I/O length - 1 2nd I/O base address (LSB) 2nd I/O base address (MSB) 2nd I/O length - 1 2nd I/O range length Interrupt request description structure TPCE_IR 1st I/O range length 2nd I/O range address 1st I/O range address
098H
EAH R
S E IO AddrLine
09AH
61H
LS
AS
N range
09CH 09EH 0A0H 0A2H 0A4H 0A6H 0A8H
F0H 01H 07H F6H 03H 01H EEH S PL M IRQ level
S = 1: Share logic active P = 1: Pulse mode IRQ supported L = 1: Level mode IRQ supported M = 0: Bit mask of IRQs present IRQ level isIRQ14
20
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Address Data 7 0AAH 0ACH 0AEH 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 12 bytes ATA secondary I/O mapped configuration I = 1: Interface byte follows D = 0: No default entry Configuration index = 3 W = 0: Wait not used R = 1: Ready active P = 0: WP not used B = 0: BVS1 and BVD2 not used IF type = 1: I/O interface CIS function Tuple code Link to next tuple Configuration table index byte TPCE_INDX 1BH CISTPL_CFTABLE ENTRY 0CH TPL_LINK 83H I D Configuration INDEX
0B0H
41H
W
RP
B interface type
Interface description field TPCE_IF
0B2H
18H
M
MS
IR IO T P
M = 0: No misc info present Feature selection byte MS = 00: No memory space TPCE_FS info IR = 1: Interrupt info present IO = 0: No I/O port info present T = 0: No timing info present P = 0: No V CC info I/O space description field R = 1: Range follows S = 1: 16-bit hosts supported TPCE_IO E = 1: 8-bit hosts supported IO AddrLines: 10 lines decoded LS = 1: Size of lengths is 1 I/O range format description byte AS = 2: Size of address is 2 byte N Range = 1: Address range - 1 1st I/O base address (LSB) 1st I/O base address (MSB) 1st I/O length - 1 2nd I/O base address (LSB) 2nd I/O base address (MSB) 2nd I/O length - 1 2nd I/O range length Interrupt request description structure TPCE_IR 1st I/O range length 2nd I/O range address 1st I/O range address
0B4H
EAH R
S E IO AddrLine
0B6H
61H
LS
AS
N range
0B8H 0BAH 0BCH 0BEH 0C0H 0C2H 0C4H
70H 01H 07H 76H 03H 01H EEH S PL M IRQ level
S = 1: Share logic active P = 1: Pulse mode IRQ supported L = 1: Level mode IRQ supported M = 0: Bit mask of IRQs present IRQ level isIRQ14
21
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Address Data 7 0C6H 0C8H 0CAH 0CCH 0CEH 0D0H 0D2H 0D4H 0D6H 0D8H 0DAH 0DCH 0DEH 0E0H 0E2H 0E4H 0E6H 0E8H 0EAH 0ECH 0EEH 0F0H 0F2H 0F4H 0F6H 0F8H 15H 15H 04H 01H 48H 49H 54H 41H 43H 48H 49H 00H 46H 4CH 41H 53H 48H 00H 31H 2EH 30H 00H FFH List end marker 14H 00H FFH CISTPL_END CISTPL_NO_LINK 65 4 3 2 1 0 Description of contents Level 1 version/product info Link length is 15h bytes PCMCIA2.0/JEIDA4.1 PCMCIA2.0/JEIDA4.1 `H' `I' `T' `A' `C' `H' `I' Null terminator `F' `L' `A' `S' `H' Null terminator `1' `.' `0' Null terminator End of device No link control tuple Link is 0 bytes End of list tuple END marker Tuple code Link to next tuple Tuple code Vender specific strings Info string 2 CIS function Tuple code Link to next tuple Major version Minor version Info string 1 CISTPL_VER_1 TPL_LINK TPPLV1_MAJOR TPPLV1_MINOR
22
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Task File register specification These registers are used for reading and writing the storage data in this card. These registers are mapped four types by the configuration of INDEX in Configuration Option register. The decoded addresses are shown as follows.
Memory map (INDEX = 0) -REG A10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A9 to A4 A3 x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 1 1 1 1 1 x x A2 0 0 0 0 1 1 1 1 0 0 1 1 1 x x A1 0 0 1 1 0 0 1 1 0 0 0 1 1 x x A0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 Offset 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H DH EH FH 8H 9H -OE = L Data register Error register Sector count register -WE = L Data register Feature register Sector count register
Sector number register Sector number register Cylinder low register Cylinder high register Drive head register Status register Cylinder low register Cylinder high register Drive head register Command register
Dup. even data register Dup. even data register Dup. odd data register Dup. error register Alt. status register Drive address register Even data register Odd data register Dup. odd data register Dup. feature register Device control register Reserved Even data register Odd data register
23
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Contiguous I/O map (INDEX = 1) -REG A10 to A4 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 1 0 1 Offset 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H DH EH FH -IORD = L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register -IOWR = L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register
Dup. even data register Dup. even data register Dup. odd data register Dup. error register Alt. status register Drive address register Dup. odd data register Dup. feature register Device control register Reserved
24
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Primary I/O map (INDEX = 2) -REG A10 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x A9 to A4 1FH 1FH 1FH 1FH 1FH 1FH 1FH 1FH 3FH 3FH A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD = L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR = L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved
Secondary I/O map (INDEX = 3) -REG A10 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x A9 to A4 17H 17H 17H 17H 17H 17H 17H 17H 37H 37H A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD = L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR = L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved
25
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
1. Data register: This register is a 16 bit register that has read/write ability, and it is used for transferring 1 sector data between the card and the host. This register can be accessed in word mode and byte mode.
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
D0 to D15
2. Error register: This register is a read only register, and it is used for analyzing the error content at the card accessing. This register is valid when the BSY bit in Status register and Alternate Status register are set to "0" (Ready). This register's bit assignment is different from operation mode and diagnostic mode. (1) Operation mode: In operation mode, error information that occurred at final command operation is stored this register. When the ERR bit in Status register and Alternate Status register are set to "1" (Error), the error content is confirmed by reading this register.
bit7 BBK bit6 UNC bit5 "0" bit4 IDNF bit3 "0" bit2 ABRT bit1 "0" bit0 AMNF
bit 7 6 4 2 0
Name BBK (Bad BlocK detected) UNC (Data ECC error) IDNF (I D Not Found) ABRT (ABoRTed command)
Function This bit is set when a Bad Block is detected in requested ID field. This bit is set when Uncorrectable error is occurred at reading the card. The requested sector ID is in error or cannot be found. This bit is set if the command has been aborted because of the card status condition. (Not ready, Write fault, Invalid command, etc.)
AMNF (Address Mark Not Found) This bit is set in case of a general error.
26
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
(2) Diagnostic mode: Diagnostic mode is available when the diagnostic command is issued. This register should be checked after the diagnostic command is issued. Diagnosed result is set this register by code.
bit7 bit6 bit5 bit4 bit3 Error code bit2 bit1 bit0
Error code 01H 02H 03H 04H 05H
Error type No error Controller error Sector buffer error ECC device error Controlling microprocessor error
3. Feature register: This register is write only register, and provides information regarding features of the drive which the host wishes to utilize.
bit7 bit6 bit5 bit4 bit3 Feature byte bit2 bit1 bit0
4. Sector count register: This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the card. In this card, the plural sector transfer is available that across the Track or Cylinder. If the value of this register is zero, a count of 256 sectors is specified. In plural sector transfer, if not successfully completed, the register contains the number of sectors which need to be transferred in order to complete the request. This register's initial value is "01H".
bit7 bit6 bit5 bit4 bit3 Sector count byte bit2 bit1 bit0
5. Sector number register: This register contains the starting sector number which is started by following sector transfer command.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Sector number byte
27
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
6. Cylinder low register: This register contains the low 8 bits of the starting cylinder address which is started by following sector transfer command.
bit7 bit6 bit5 bit4 bit3 Cylinder low byte bit2 bit1 bit0
7. Cylinder low register: This register contains the low 8 bits of the starting cylinder address which is started by following sector transfer command.
bit7 bit6 bit5 bit4 bit3 Cylinder high byte bit2 bit1 bit0
8. Drive head register: This register contains the high 8 bits of the starting cylinder address which is started by following sector transfer command.
bit7 1 bit6 LBA bit5 1 bit4 DRV bit3 Head number bit2 bit1 bit0
Note: DRV: Drive number Head number: Head number
bit 7 6
Name 1 LBA
Function This bit is set to "1". LBA is a flag to select either Cylinder / Head / Sector (CHS) or Logical Block Address (LBA) mode. When LBA=0, CHS mode is selected. When LBA=1, LBA mode is selected. In LBA mode, the Logical Block Address is interrupted as follows: LBA07-LBA00 : Sector Number Register D7-D0. LBA15-LBA08 : Cylinder Low Register D7-D0. LBA23-LBA16 : Cylinder High Register D7-D0. LBA27-LBA24 : Drive / Head Register bits HS3-HS0. This bit is set to "1". This bit is used for selecting the Master (Card 0) and Slave (Card 1) in Master/Slave organization. The card is set to be Card 0 or 1 by using DRV# of the Socket and Copy register. This bit is used for selecting the Head number for the following command. Bit 3 is MSB.
5 4
1 DRV (DRiVe select)
3 to 0 Head number
28
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
9. Status register: This register is read only register, and it indicates the card status of command execution. Other bits are invalid when BSY bit is "1". When this register is read, -IREQ is negated. And when host writes the command code to Command register, bit 0, 4 and 6 are cleared and bit 7 is set.
bit7 BSY bit6 DRDY bit5 DWF bit4 DSC bit3 DRQ bit2 CORR bit1 IDX bit0 ERR
bit 7 6
Name BSY (BuSY) DRDY (Drive ReaDY)
Function This bit is set when the card internal operation is executing. When this bit is set to "1", other bits in this register are invalid. If this bit and DSC bit are set to "1", the card is capable of receiving the read or write or seek requests. If this bit is set to "0", the card prohibits these requests. This bit is set if this card indicates the write fault status. This bit is set when the drive seek complete. This bit is set when the information can be transferred between the host and Data register. This bit is cleared when the card receives the other command. This bit is set when a correctable data error has been occurred and the data has been corrected. This bit is always set to "0". This bit is set when the previous command has ended in some type of error. The error information is set in the other Status register or Error register. This bit is cleared by the next command.
5 4 3
DWF (Drive Write Fault) DSC (Drive Seek Complete) DRQ (Data ReQuest)
2 1 0
CORR (CORRected data IDX (InDeX) ERR (ERRor)
10. Alternate status register: This register is the same as Status register in physically, so the bit assignment refers to previous item of Status register. But this register is different from Status register that -IREQ is not negated when data read.
29
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
11. Command register: This register is write only register, and it is used for writing the command at executing the drive operation. The command code written in the command register, after the parameter is written in the Task File during the card is Ready state.
Used parameter Command Check power mode Execute drive diagnostic Format track Identify Drive Idle Idle immediate Initialize drive parameters Read buffer Read multiple Read long sector Read sector Read verify sector Recalibrate Seek Set features Set multiple mode Set sleep mode Stand by Stand by immediate Write buffer Write long sector Write multiple Write sector Write verify Command code E5H or 98H 90H 50H ECH E3H or 97H E1H or 95H 91H E4H C4H 22H or 23H 20H or 21H 40H or 41H 1XH 7XH EFH C6H E6H or 99H E2H or 96H E0H or 94H E8H 32H or 33H C5H 30H or 31H 3CH FR N N N N N N N N N N N N N N Y N N N N N N N N N SC N N Y N Y N Y N Y N Y Y N N N Y N N N N N Y Y Y SN N N N N N N N N Y Y Y Y N Y N N N N N N Y Y Y Y CY N N Y N N N N N Y Y Y Y N Y N N N N N N Y Y Y Y DR Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y HD N N Y N N N Y N Y Y Y Y N Y N N N N N N Y Y Y Y LBA N N Y N N N N N Y Y Y Y N Y N N N N N N Y Y Y Y
Note: FR: Feature register SC: Sector Count register SN: Sector Number register CY: Cylinder register DR: DRV bit of Drive Head register HD: Head Number of Drive Head register LBA: Logical Block Address Mode Supported Y: The register contains a valid parameter for this command. N: The register does not contain a valid parameter for this command.
30
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
12. Device control register: This register is write only register, and it is used for controlling the card interrupt request and issuing an ATA soft reset to the card.
bit7 x bit6 x bit5 x bit4 x bit3 1 bit2 SRST bit1 nIEN bit0 0
bit
Name
Function don't care This bit is set to "1". This bit is set to "1" in order to force the card to perform Task File Reset operation. This does not change the Card Configuration registers as a Hardware Reset does. The card remains in Reset until this bit is reset to "0". This bit is used for enabling -IREQ. When this bit is set to "0", -IREQ is enabled. When this bit is set to "1", -IREQ is disabled. This bit is set to "0".
7 to 4 x 3 2 1 SRST (Software ReSeT)
1 0
nIEN (Interrupt ENable) 0
13. Drive Address register: This register is read only register, and it is used for confirming the drive status. This register is provides for compatibility with the AT disk drive interface. It is recommended that this register not be mapped into the host's I/O space because of potential conflicts on bit7.
bit7 x bit6 nWTG bit5 nHS3 bit4 nHS2 bit3 nHS1 bit2 nHS0 bit1 nDS1 bit0 nDS0
bit 7 6
Name x nWTG (WriTing Gate)
Function This bit is unknown This bit is unknown These bits is the negative value of Head Select bits (bit 3 to 0) in Drive/Head register. This bit is unknown This bit is unknown
5 to 2 nHS3-0 (Head Select3-0) 1 0 nDS1 (Idrive Select1) nDS0 (Idrive Select0)
31
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
ATA Command specifications This table summarizes the ATA command set with the paragraphs. Following shows the support commands and command codes which are written in command registers. ATA Command Set
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Command set Check power mode Execute drive diagnostic Format track Identify Drive Idle Idle immediate Initialize drive parameters Read buffer Read multiple Read long sector Read sector (s) Read verify sector (s) Recalibrate Seek Set features Set multiple mode Set sleep mode Stand by Stand by immediate Write buffer Write long sector Write multiple Write sector Write verify Code E5H or 98H 90H 50H ECH E3H or 97H E1H or 95H 91H E4H C4H 22H, 23H 20H, 21H 40H, 41H 1XH 7XH EFH C6H E6H or 99H E2H or 96H E0H or 94H E8H 32H or 33H C5H 30H or 31H 3CH FR -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y -- -- -- -- -- -- -- -- -- SC -- -- Y -- Y -- Y -- Y -- Y Y -- -- -- Y -- -- -- -- -- Y Y Y SN -- -- -- -- -- -- -- -- Y Y Y Y -- Y -- -- -- -- -- -- Y Y Y Y CY -- -- Y -- -- -- -- -- Y Y Y Y -- Y -- -- -- -- -- -- Y Y Y Y DR Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y HD -- -- Y -- -- -- Y -- Y Y Y Y -- Y -- -- -- -- -- -- Y Y Y Y LBA -- -- Y -- -- -- -- -- Y Y Y Y -- Y -- -- -- -- -- -- Y Y Y Y
Note: FR: Feature Register SC: Sector Count register (00H to FFH) SN: Sector Number register (01H to 20H) CY: Cylinder Low/High register (to) DR: Drive bit of Drive/Head register HD: Head No.(0 to 3) of Drive/Head register NH: No. of Heads Y: Set up --: Not set up
32
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
1. Check Power Mode (code: E5H or 98H): This command checks the power mode. 2. Execute Drive Diagnostic (code: 90H): This command performs the internal diagnostic tests implemented by the Card. 3. Format Track (code: 50H): This command writes the desired head and cylinder of the selected drive. But selected sector data is not exchange. This card excepts a sector buffer of data from the host to follow the command with same protocol as the Write Sector command. 4. Identify Drive (code: ECH): This command enables the host to receive parameter information from the Card. Identify Drive Information
Word address Default value 0 1 2 3 4 5 6 7 to 8 9 10 to 19 20 21 22 23 to 46 47 48 49 50 51 52 53 to 58 59 60 to 61 62 to 255 848AH XXXX 000H 00XXH 0000H XXXX XXXX XXXX 0000H 0000H 0002H 0002H 0004H XXXX 0001H 0000H 0200H 0000H 1000H 0000H 0000H 010XH XXXX 0000H Total bytes 2 2 2 2 2 2 2 2 2 20 2 2 2 48 2 2 2 2 2 2 12 2 4 388 Data field type information General configuration bit-significant information General configuration bit-significant information Reserved Default number of heads Number of unformatted bytes per track Number of unformatted bytes per sector Default number of sectors per track Number of sectors per card (Word7 = MSW, Word8 = LSW) Reserved Reserved Buffer type (dual ported) Buffer size in 512 byte increments # of ECC bytes passed on Read/Write Long Commands Firmware revision in ASCII etc. Maximum of 1 sector on Read/Write Multiple command Double Word not supported Capabilities: DMA NOT Supported (bit 8), LBA supported (bit9) Reserved PIO data transfer cycle timing mode 1 DMA data transfer cycle timing mode not Supported Reserved Multiple sector setting is valid Total number of sectors addressable in LBA Mode Reserved
33
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
5. Idle (code: E3H or 97H): This command causes the Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If sector count is non-zero, the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is disabled. 6. Idle Immediate (code: E1H or 95H): This command causes the Card to set BSY, enter the Idle (Read) mode, clear BSY and generate an interrupt. 7. Initialize Drive Parameters (code: 91H): This command enables the host to set the number of sectors per track and the number of heads per cylinder. 8. Read Buffer (code: E4H): This command enables the host to read the current contents of the card's sector buffer. 9. Read Multiple (code: C4H): This command performs similarly to the Read Sectors command. Interrupts are not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. 10. Read Long Sector (code: 22H or 23H): This command performs similarly to the Read Sector(s) command except that it returns 516 bytes of data instead of 512 bytes. 11. Read Sector(s) (code: 20H, 21H): This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. 12. Read Verify Sector (code: 40H or 41H): This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host . 13. Recalibrate (code: 1XH): This command is effectively a NOP command to the Card and is provided for compatibility purposes. 14. Seek (code: 7XH): This command is effectively a NOP command to the Card although it does perform a range check. 15. Set Features (code: EFH): This command is used by the host to establish or select certain features. 16. Set Multiple Mode (code: C6H): This command enables the Card to perform Read and Write Multiple operations and establishes the block count for these commands. 17. Set Sleep Mode (code: E6H or 99H): This command causes the Card to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. 18. Stand By (code: E2H or 96H): This command causes the Card to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. 19. Stand By Immediate (code: E0H or 94H): This command causes the Card to set BSY, enter the Sleep mode(which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. 20. Write Buffer (code: E8H): This command enables the host to overwrite contents of the Card's sector buffer with any data pattern desired.
34
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
21. Write Long Sector (code: 32H or 33H): This command is provided for compatibility purposes and is similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes. 22. Write Multiple (code: C5H): This command is similar to the Write Sectors command. Interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors defined by Set Multiple command. 23. Write Sector(s) (code: 30H or 31H): This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. 24. Write Verify (code: 3CH): This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written.
35
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Sector Transfer Protocol 1. Sector read: 1 sector read procedure after the card configured I/O interface is shown as follows.
Start Set the cylinder low / high register
I/O Access,INDEX=1
Set the head No.of drive head register (1)Set the logical sector number Set the sector number register Set "01H" in sector count register
Set "20H" in Command register
(2)
Read the status register (3) N '58H"? Y Read 256 times the data register (512 bytes) (4)Burst data transfer
Read the status register N (5) '50H"? Y Wait the command input
36
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
(1) A to A10 -CE1 -CE2 -IOWR -IORD D0 to D15 -IREQ 01H20H 80H 58H Data Transfer 80H 50H (2) 7H (3) 7H 0H (4) 0H (5) 7H 7H
4H 5H 6H 3H 2H 7H
37
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
2. Sector write: 1 sector write procedure after the card configured I/O interface is shown as follows.
Start Set the cylinder low / high register
I/O Access, INDEX=1
Set the head No.of drive head register (1) Set the logical sector number Set the sector number register Set "01H" in sector count register
Set "30H" in command register
(2)
Read the status register (3) N '58H"? Y Write 256 times the data register (512 bytes) (4) Burst data transfer
Read the status register N (5) '50H"? Y Wait the command input
38
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
(1) A to A10 -CE1 -CE2 -IOWR -IORD D0 to D15 -IREQ 01H30H 80H 58H Data Transfer 80H 50H (2) 7H (3) 7H 0H (4) 0H 7H (5) 7H
4H 5H 6H 3H 2H 7H
39
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Absolute Maximum Ratings
Parameter All input/output voltages VCC voltage Operating temperature range Storage temperature range Note: Symbol Vin, Vout VCC Topr Tstg Value -0.3 to VCC + 0.3 -0.3 to +6.5 0 to +60 -20 to +65 Unit V V C C Note 1
1. Vin, Vout min = -2.0 V for pulse width 20 ns.
Recommended DC Operating Conditions
Parameter Operating temperature VCC voltage Symbol Ta VCC Min 0 4.5 Typ 25 5.0 Max 60 5.5 Unit C V Note
Capacitance (Ta = 25C, f = 1MHz)
Parameter Input capacitance Output capacitance Symbol Cin Cout Min -- -- Typ -- -- Max 35 35 Unit pF pF Test conditions Vin = 0 V Vout = 0 V
System Performance
Item Set up times (Reset to ready) Set up times (Sleep to idle) Data transfer rate to/from host Controller overhead (Command to DRQ) Data transfer cycle end to ready (Sector write) Performance 250 ms (max) 2 ms (max) 8 MB/s burst 2 ms (max) 2 ms (typ)
40
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
DC Characteristics-1 (Ta = 0 to +60C, VCC = 5.0 V 10%)
Parameter Input leakage current Input voltage (CMOS) Symbol ILI VIL VIH Input voltage (schmitt trigger) VIL VIH Output voltage VOL VOH Note: 1. Except pulled up input pin. Min -- -0.3 4.0 -- -- -- Typ -- -- -- 2.0 2.8 -- Max 1 0.8 Unit A V Test conditions Vin = GND to V CC Note 1
VCC + 0.2 V -- -- 0.4 -- V V V V IOL = 8 mA IOH = -8 mA
VCC - 0.8 --
DC Characteristics-2 (Ta = 0 to +60C, VCC = 5.0 V 10%)
Parameter Sleep/standby current Sector read current Symbol ISP1 ICCR (DC) ICCR (Peak) Sector write current ICCW (DC) ICCW (Peak) Typ 2 70 100 70 100 Max 3 100 150 100 150 mA CMOS level (control signal = V CC - 0.2 V) between sector write transfer Unit mA mA Test conditions CMOS level (control signal = V CC - 0.2 V) CMOS level (control signal = V CC - 0.2 V) between sector read transfer
41
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
DC Current Waveform (Example of sector read or write: V CC = 5 V, Ta = 25C)
Sector Read
Current
ICCR(Peak) ICCR(DC) 0 Time
Command write
Complete of sector read
Sector Write
Current
ICCW(DC) 0 Time
ICCW(Peak)
Command write
Complete of sector write
42
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
AC Characteristics (Ta = 0 to +60C, VCC = 5 V 10%)
Attribute Memory Read AC Characteristics
250 ns Parameter Read cycle time Address access time -CE access time -OE access time Output disable time (-CE) Output disable time (-OE) Output enable time (-CE) Output enable time (-OE) Data valid time (A) Address setup time Address hold time -CE setup time -CE hold time Symbol tCR ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tv(A) tsu(A) th(A) Min 250 -- -- -- -- -- 5 5 0 30 20 0 20 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- 250 250 125 100 100 -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(CE) th(CE)
Attribute Memory Read Timing
tCR A0 to A10, -REG ta(A) ta(CE) -CE2/-CE1 tsu(A) -OE ten(OE) ten(CE) D0 to D15 Valid Output -WE, -IOWR, -IORD : High Fix tdis(OE) tsu(CE) ta(OE) th(CE) tdis(CE) th(A) tv(A)
43
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Attribute Memory Write AC Characteristics
250 ns Parameter Write cycle time Write pulse time Address setup time Address setup time (-WE) -CE setup time (-WE) Data setup time (-WE) Data hold time Write recover time Output disable time (-WE) Output disable time (-OE) Output enable time (-WE) Output enable time (-OE) Output enable setup time (-WE) Output enable hold time (-WE) -CE setup time -CE hold time Symbol tCW tw(WE) tsu(A) tsu(A-WEH) tsu(CE-WEH) tsu(D-WEH) th(D) trec(WE) tdis(WE) tdis(OE) ten(WE) ten(OE) tsu(OE-WE) th(OE-WE) Min 250 150 30 180 180 80 30 30 -- -- 5 5 10 10 0 20 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- 100 100 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(CE) th(CE)
Attribute Memory Write Timing
tCW A0 to A10, -REG tsu(CE-WEH) -CE2/-CE1 -OE tsu(A) -WE tsu(OE-WE) tsu(D-WEH) D0 to D15(Din) tdis(OE) D0 to D15(Dout) ten(WE) -IOWR, -IORD : High Fix tdis(WE) Input Data ten(OE) tw(WE) trec(WE) th(OE-WE) th(D) tsu(A-WEH) tsu(CE) th(CE)
44
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
I/O Access Read AC Characteristics
Parameter Data delay after -IORD Data hold following -IORD -IORD pulse width Address setup before -IORD Address hold following -IORD -CE setup before -IORD -CE hold following -IORD -REG setup before -IORD -REG hold following -IORD -INPACK delay falling from -IORD -INPACK delay rising from -IORD -IOIS16 delay falling from address -IOIS16 delay rising from address Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tsuREG(IORD) thREG(IORD) Min -- 0 165 70 20 5 20 5 0 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 100 -- -- -- -- -- -- -- -- 45 45 35 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tdfINPCAK(IORD) 0 tdrINPACK(IORD) -- tdfIOIS16(IORD) tdrIOIS16(IORD) -- --
I/O Access Read Timing
A0 to A10 thA(IORD) tsuREG(IORD) thREG(IORD) -REG tsuCE(IORD) -CE2/-CE1 tw(IORD) -IORD tsuA(IORD) -INPACK tdfIOIS16(ADR) tdfINPACK(IORD) -IOIS16 th(IORD) D0 to D15 td(IORD) -WE, -OE, -IOWR : High Fix
Valid Output
thCE(IORD)
tdrINPACK(IORD)
tdrIOIS16(ADR)
45
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
I/O Access Write AC Characteristics
Parameter Data setup before -IOWR Data hold following -IOWR -IOWR pulse width Address setup before -IOWR Address hold following -IOWR -CE setup before -IOWR -CE hold following -IOWR -REG setup before -IOWR -REG hold following -IOWR -IOIS16 delay falling from address -IOIS16 delay rising from address Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tsuREG(IOWR) thREG(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR) Min 60 30 165 70 20 5 20 5 0 -- -- Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- 35 35 Unit ns ns ns ns ns ns ns ns ns ns ns
I/O Access Write Timing
A0 to A10 thA(IOWR) tsuREG(IOWR) thREG(IOWR) -REG tsuCE(IOWR) -CE2/-CE1 tsuA(IOWR) tw(IOWR) -IOWR tdfIOIS16(ADR) -IOIS16 tsu(IOWR) D0 to D15 Data In th(IOWR) tdrIOIS16(ADR) thCE(IOWR)
-WE, -OE, -IORD : High Fix
46
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Common Memory Access Read AC Characteristics
Parameter -CE access time Output disable time (-OE) Address setup time Address hold time -CE setup time -CE hold time Symbol ta(OE) tdis(OE) tsu(A) th(A) tsu(CE) th(CE) Min -- -- 30 20 0 20 Typ -- -- -- -- -- -- Max 125 100 -- -- -- -- Unit ns ns ns ns ns ns
Common Access Read Timing
A0 to A10 tsu(A) -REG th(A)
-CE2/-CE1 tsu(CE) ta(OE) -OE tdis(OE) D0 to D15
Valid Output
th(CE)
-WE, -IORD, -IOWR : High Fix
47
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Common Memory Access Write AC Characteristics
Parameter Data setup time (-WE) Data hold time Write pulse time Address setup time -CE setup time Write recover time -CE hold following -WE Symbol tsu(D-WEH) th(D) tw(WE) tsu(A) tsu(CE) trec(WE) th(CE) Min 80 30 150 30 0 30 20 Typ -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
Common Access Write Timing
A0 to A10
-REG tsu(CE) -CE2/-CE1 tsu(A) tw(WE) -WE tsu(D-WEH) D0 to D15 th(D) th(CE) trec(WE)
Data In
-IOWR, -IORD, -OE : High Fix
48
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Reset Characteristics Hard Reset Characteristics
Parameter Reset setup time -CE recover time VCC rising up time VCC falling down time Reset pulse width Symbol tSU(RESET) tREC(VCC) tpr tpf tW(RESET) Min 250 1 0.1 3 10 Typ -- -- -- -- -- -- -- Max -- -- 100 300 -- -- -- Unit ms s ms ms s ms ms Test conditions
th(Hi-ZRESET) 1 ts(Hi-ZRESET) 0
Hard Reset Timing
tpr 90% Vcc 10% 90% trec(Vcc) 10% tpf
-CE1, -CE2 th(Hi-ZRESET) High-Z tsu(RESET) tw(RESET) +RESET Low ts(Hi-ZRESET) High-Z
49
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Power on Reset Characteristics All card status are reset automatically when V CC voltage goes over about 2.3 V.
Parameter -CE setup time VCC rising up time Symbol tSU(VCC) tpr Min 250 0.1 Typ -- -- Max -- 100 Unit ms ms Test conditions
Power on Reset Timing
tpr Vcc tsu(vcc)
-CE1, -CE2
Attention for Card Use
* In the reset or power off, all register informations are cleared. * All card status are cleared automatically when Vcc voltage turns below about 2.5V. * After the card hard reset, soft reset, or power on reset, the card cannot access during +READY pin is "low" level. * Please notice that the card insertion/removal should be executed after card internal operations completed (status register bit 7 turns from "1" to "0").
50
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Physical Outline
Unit: mm 54.00 0.10 5.0 (max)
85.60 0.20
10.0 min
3.3 0.1 34pin Upper side 1pin 1.27 0.1 68pin Lower side 1.27 0.1 41.91 (Reference value) 35pin
51
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
52
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Revision Record
Rev. Date 0.0 1.0 Contents of Modification Drawn by T. Kikuchi T. Kikuchi Approved by K. Inoue K. Inoue Jun. 31, 1996 Initial issue Nov. 20, 1996 Change of description for Card Pin Explanation Change of Socket and Copy register Change of CIS informations Change of Task File register specification Sector Transfer Protocol Change o timing w veforms: Sector read and Sector w ite f a r System Performance Start up times max: 2 s (15MB)/10 s (75MB) to 250 ms DC Characteristics (1) Addition of note1 DC Characteristics (2) ISP1 typ: 1 mA to 2 mA ISP1 max: 2 mA to 3 mA AC Characteristics Common Memory Access Write AC Characteristics Addition of th(CE) min: 20 ns Change of Common Access Write Timing Power on Reset Characteristics tpr max: 300 ms to 100 ms Physical Outline Card width: 5.0 0.20 to 5.0 (max) Change of description for Card Pin Explanation Change of description for Card Function Explanation Change of Task File register specification AC Characteristics Reset Characteristics tSU(RESET) min: 20 ms to 250 ms Power on Reset Characteristics tSU(VCC) min: 20 ms to 250 ms Change of Physical Outline
2.0
Feb. 28, 1997
53

▲Up To Search▲

Price & Availability of HB286075A1

	To Download HB286075A1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .